From 1b5afb45838e603fa6780762eb8cc59246dc2d81 Mon Sep 17 00:00:00 2001
From: IlyaOvodov <b@ovdv.ru>
Date: Tue, 08 May 2018 11:09:35 +0000
Subject: [PATCH] Output improvements for detector results: When printing detector results, output was done in random order, obfuscating results for interpreting. Now: 1. Text output includes coordinates of rects in (left,right,top,bottom in pixels) along with label and score 2. Text output is sorted by rect lefts to simplify finding appropriate rects on image 3. If several class probs are > thresh for some detection, the most probable is written first and coordinates for others are not repeated 4. Rects are imprinted in image in order by their best class prob, so most probable rects are always on top and not overlayed by less probable ones 5. Most probable label for rect is always written first Also: 6. Message about low GPU memory include required amount
---
src/gemm.c | 232 +++++++++++++++++++++++++++++++++++++++++++++++++--------
1 files changed, 199 insertions(+), 33 deletions(-)
diff --git a/src/gemm.c b/src/gemm.c
index a923beb..317fd65 100644
--- a/src/gemm.c
+++ b/src/gemm.c
@@ -5,6 +5,28 @@
#include <stdio.h>
#include <math.h>
+void gemm_bin(int M, int N, int K, float ALPHA,
+ char *A, int lda,
+ float *B, int ldb,
+ float *C, int ldc)
+{
+ int i,j,k;
+ for(i = 0; i < M; ++i){
+ for(k = 0; k < K; ++k){
+ char A_PART = A[i*lda+k];
+ if(A_PART){
+ for(j = 0; j < N; ++j){
+ C[i*ldc+j] += B[k*ldb+j];
+ }
+ } else {
+ for(j = 0; j < N; ++j){
+ C[i*ldc+j] -= B[k*ldb+j];
+ }
+ }
+ }
+ }
+}
+
float *random_matrix(int rows, int cols)
{
int i;
@@ -49,22 +71,150 @@
gemm_cpu( TA, TB, M, N, K, ALPHA,A,lda, B, ldb,BETA,C,ldc);
}
-void gemm_nn(int M, int N, int K, float ALPHA,
- float *A, int lda,
- float *B, int ldb,
- float *C, int ldc)
+#if (defined(__AVX__) && defined(__x86_64__)) || defined(_WIN64)
+
+#define OSXSAVEFlag (1UL<<27)
+#define AVXFlag ((1UL<<28)|OSXSAVEFlag)
+#define FMAFlag ((1UL<<12)|AVXFlag|OSXSAVEFlag)
+#define CLMULFlag ((1UL<< 1)|AVXFlag|OSXSAVEFlag)
+#define VAESFlag ((1UL<<25)|AVXFlag|OSXSAVEFlag)
+
+#include <stdint.h>
+
+#ifdef _WIN64
+#include <intrin.h>
+#include <ammintrin.h>
+#include <immintrin.h>
+#include <smmintrin.h>
+
+#else // Linux GCC/Clang
+#include <x86intrin.h>
+#include <ammintrin.h>
+#include <immintrin.h>
+#include <smmintrin.h>
+#include <cpuid.h>
+
+void asm_cpuid(uint32_t* abcd, uint32_t eax)
{
- int i,j,k;
- for(i = 0; i < M; ++i){
- for(k = 0; k < K; ++k){
- register float A_PART = ALPHA*A[i*lda+k];
- for(j = 0; j < N; ++j){
- C[i*ldc+j] += A_PART*B[k*ldb+j];
- }
- }
- }
+ uint32_t ebx = 0, edx = 0, ecx = 0;
+
+ // EBX is saved to EDI and later restored
+ __asm__("movl %%ebx, %%edi;"
+ "cpuid;"
+ "xchgl %%ebx, %%edi;"
+ : "=D"(ebx),
+ "+a"(eax), "+c"(ecx), "=d"(edx));
+
+ abcd[0] = eax;
+ abcd[1] = ebx;
+ abcd[2] = ecx;
+ abcd[3] = edx;
}
+#endif
+
+int simd_detect_x86(unsigned int idFeature)
+{
+ uint32_t regs[4]; // EAX, EBX, ECX, EDX;
+#ifdef _WIN32
+ __cpuid(regs, 0);
+ if (regs[0] > 1U) __cpuid(regs, 1);
+#else
+ __get_cpuid(0, ®s[0], ®s[1], ®s[2], ®s[3]);
+ if(regs[0] > 1U) __get_cpuid(1, ®s[0], ®s[1], ®s[2], ®s[3]);
+#endif
+
+ if ((regs[2] & idFeature) != idFeature)
+ return 0;
+ return 1;
+}
+
+int is_fma_avx() {
+ static int result = -1;
+ if (result == -1) {
+ result = simd_detect_x86(AVXFlag);
+ if (result == 1) printf(" Used AVX \n");
+ else printf(" Not used AVX \n");
+ }
+ return result;
+}
+
+// https://software.intel.com/sites/landingpage/IntrinsicsGuide
+void gemm_nn(int M, int N, int K, float ALPHA,
+ float *A, int lda,
+ float *B, int ldb,
+ float *C, int ldc)
+{
+ int i, j, k;
+ if (is_fma_avx() == 1) { // AVX
+ for (i = 0; i < M; ++i) {
+ for (k = 0; k < K; ++k) {
+ float A_PART = ALPHA*A[i*lda + k];
+ __m256 a256, b256, c256, result256; // AVX
+ a256 = _mm256_set1_ps(A_PART);
+ for (j = 0; j < N - 8; j += 8) {
+ b256 = _mm256_loadu_ps(&B[k*ldb + j]);
+ c256 = _mm256_loadu_ps(&C[i*ldc + j]);
+ // FMA - Intel Haswell (2013), AMD Piledriver (2012)
+ //result256 = _mm256_fmadd_ps(a256, b256, c256);
+ result256 = _mm256_mul_ps(a256, b256);
+ result256 = _mm256_add_ps(result256, c256);
+ _mm256_storeu_ps(&C[i*ldc + j], result256);
+ }
+
+ int prev_end = (N % 8 == 0) ? (N - 8) : (N / 8) * 8;
+ for (j = prev_end; j < N; ++j)
+ C[i*ldc + j] += A_PART*B[k*ldb + j];
+ }
+ }
+ }
+ else {
+ for (i = 0; i < M; ++i) {
+ for (k = 0; k < K; ++k) {
+ register float A_PART = ALPHA*A[i*lda + k];
+ for (j = 0; j < N; ++j) {
+ C[i*ldc + j] += A_PART*B[k*ldb + j];
+ }
+ /* // SSE
+ __m128 a128, b128, c128, result128; // SSE
+ a128 = _mm_set1_ps(A_PART);
+ for (j = 0; j < N - 4; j += 4) {
+ b128 = _mm_loadu_ps(&B[k*ldb + j]);
+ c128 = _mm_loadu_ps(&C[i*ldc + j]);
+ //result128 = _mm_fmadd_ps(a128, b128, c128);
+ result128 = _mm_mul_ps(a128, b128);
+ result128 = _mm_add_ps(result128, c128);
+ _mm_storeu_ps(&C[i*ldc + j], result128);
+ }
+
+ int prev_end = (N % 4 == 0) ? (N - 4) : (N / 4) * 4;
+ for (j = prev_end; j < N; ++j){
+ C[i*ldc + j] += A_PART*B[k*ldb + j];
+ }
+ */
+ }
+ }
+ }
+}
+#else
+
+void gemm_nn(int M, int N, int K, float ALPHA,
+ float *A, int lda,
+ float *B, int ldb,
+ float *C, int ldc)
+{
+ int i, j, k;
+ for (i = 0; i < M; ++i) {
+ for (k = 0; k < K; ++k) {
+ register float A_PART = ALPHA*A[i*lda + k];
+ for (j = 0; j < N; ++j) {
+ C[i*ldc + j] += A_PART*B[k*ldb + j];
+ }
+ }
+ }
+}
+#endif // __x86_64
+
void gemm_nt(int M, int N, int K, float ALPHA,
float *A, int lda,
float *B, int ldb,
@@ -129,14 +279,19 @@
C[i*ldc + j] *= BETA;
}
}
- if(!TA && !TB)
- gemm_nn(M, N, K, ALPHA,A,lda, B, ldb,C,ldc);
- else if(TA && !TB)
- gemm_tn(M, N, K, ALPHA,A,lda, B, ldb,C,ldc);
- else if(!TA && TB)
- gemm_nt(M, N, K, ALPHA,A,lda, B, ldb,C,ldc);
- else
- gemm_tt(M, N, K, ALPHA,A,lda, B, ldb,C,ldc);
+
+ int t;
+ #pragma omp parallel for
+ for (t = 0; t < M; ++t) {
+ if (!TA && !TB)
+ gemm_nn(1, N, K, ALPHA, A + t*lda, lda, B, ldb, C + t*ldc, ldc);
+ else if (TA && !TB)
+ gemm_tn(1, N, K, ALPHA, A + t, lda, B, ldb, C + t*ldc, ldc);
+ else if (!TA && TB)
+ gemm_nt(1, N, K, ALPHA, A + t*lda, lda, B, ldb, C + t*ldc, ldc);
+ else
+ gemm_tt(1, N, K, ALPHA, A + t, lda, B, ldb, C + t*ldc, ldc);
+ }
}
#ifdef GPU
@@ -150,8 +305,9 @@
float *C_gpu, int ldc)
{
cublasHandle_t handle = blas_handle();
+ cudaError_t stream_status = cublasSetStream(handle, get_cuda_stream());
cudaError_t status = cublasSgemm(handle, (TB ? CUBLAS_OP_T : CUBLAS_OP_N),
- (TA ? CUBLAS_OP_T : CUBLAS_OP_N), N, M, K, &ALPHA, B_gpu, ldb, A_gpu, lda, &BETA, C_gpu, ldc);
+ (TA ? CUBLAS_OP_T : CUBLAS_OP_N), N, M, K, &ALPHA, B_gpu, ldb, A_gpu, lda, &BETA, C_gpu, ldc);
check_error(status);
}
@@ -276,6 +432,7 @@
int test_gpu_blas()
{
+ /*
test_gpu_accuracy(0,0,10,576,75);
test_gpu_accuracy(0,0,17,10,10);
@@ -288,19 +445,28 @@
test_gpu_accuracy(0,1,1000,10,100);
test_gpu_accuracy(1,1,1000,10,100);
- test_gpu_accuracy(0,0,10,10,10);
+ test_gpu_accuracy(0,0,10,10,10);
- time_ongpu(0,0,64,2916,363);
- time_ongpu(0,0,64,2916,363);
- time_ongpu(0,0,64,2916,363);
- time_ongpu(0,0,192,729,1600);
- time_ongpu(0,0,384,196,1728);
- time_ongpu(0,0,256,196,3456);
- time_ongpu(0,0,256,196,2304);
- time_ongpu(0,0,128,4096,12544);
- time_ongpu(0,0,128,4096,4096);
+ time_ongpu(0,0,64,2916,363);
+ time_ongpu(0,0,64,2916,363);
+ time_ongpu(0,0,64,2916,363);
+ time_ongpu(0,0,192,729,1600);
+ time_ongpu(0,0,384,196,1728);
+ time_ongpu(0,0,256,196,3456);
+ time_ongpu(0,0,256,196,2304);
+ time_ongpu(0,0,128,4096,12544);
+ time_ongpu(0,0,128,4096,4096);
+ */
+ time_ongpu(0,0,64,75,12544);
+ time_ongpu(0,0,64,75,12544);
+ time_ongpu(0,0,64,75,12544);
+ time_ongpu(0,0,64,576,12544);
+ time_ongpu(0,0,256,2304,784);
+ time_ongpu(1,1,2304,256,784);
+ time_ongpu(0,0,512,4608,196);
+ time_ongpu(1,1,4608,512,196);
-return 0;
+ return 0;
}
#endif
--
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