From c2a8cc2ad3f4b31243cbf577440ee45bafcc7f92 Mon Sep 17 00:00:00 2001
From: AlexeyAB <alexeyab84@gmail.com>
Date: Thu, 16 Aug 2018 00:02:54 +0000
Subject: [PATCH] Fix GCC compile
---
src/gemm.c | 151 ++++++++++++++++++++++++++++++++++++++++++-------
1 files changed, 128 insertions(+), 23 deletions(-)
diff --git a/src/gemm.c b/src/gemm.c
index d233e9c..6a34da5 100644
--- a/src/gemm.c
+++ b/src/gemm.c
@@ -306,18 +306,13 @@
#if (defined(__AVX__) && defined(__x86_64__)) || defined(_WIN64)
-#define OSXSAVEFlag (1UL<<27)
-#define AVXFlag ((1UL<<28)|OSXSAVEFlag)
-#define FMAFlag ((1UL<<12)|AVXFlag|OSXSAVEFlag)
-#define CLMULFlag ((1UL<< 1)|AVXFlag|OSXSAVEFlag)
-#define VAESFlag ((1UL<<25)|AVXFlag|OSXSAVEFlag)
-
#ifdef _WIN64
#include <intrin.h>
#include <ammintrin.h>
#include <immintrin.h>
#include <smmintrin.h>
+#if defined(_MSC_VER) && _MSC_VER <= 1900
static inline __int32 _mm256_extract_epi64(__m256i a, const int index) {
return a.m256i_i64[index];
}
@@ -325,13 +320,14 @@
static inline __int32 _mm256_extract_epi32(__m256i a, const int index) {
return a.m256i_i32[index];
}
+#endif
static inline float _castu32_f32(uint32_t a) {
return *((float *)&a);
}
static inline float _mm256_extract_float32(__m256 a, const int index) {
- return _castu32_f32(_mm256_extract_epi32(_mm256_castps_si256(a), index));
+ return a.m256_f32[index];
}
#else // Linux GCC/Clang
@@ -365,35 +361,121 @@
abcd[2] = ecx;
abcd[3] = edx;
}
-
#endif
-int simd_detect_x86(unsigned int idFeature)
-{
- uint32_t regs[4]; // EAX, EBX, ECX, EDX;
+
+
#ifdef _WIN32
- __cpuid(regs, 0);
- if (regs[0] > 1U) __cpuid(regs, 1);
+// Windows
+#define cpuid(info, x) __cpuidex(info, x, 0)
#else
- __get_cpuid(0, ®s[0], ®s[1], ®s[2], ®s[3]);
- if(regs[0] > 1U) __get_cpuid(1, ®s[0], ®s[1], ®s[2], ®s[3]);
+// GCC Intrinsics
+void cpuid(int info[4], int InfoType) {
+ __cpuid_count(InfoType, 0, info[0], info[1], info[2], info[3]);
+}
#endif
- if ((regs[2] & idFeature) != idFeature)
- return 0;
- return 1;
+
+// Misc.
+static int HW_MMX, HW_x64, HW_RDRAND, HW_BMI1, HW_BMI2, HW_ADX, HW_PREFETCHWT1;
+static int HW_ABM; // Advanced Bit Manipulation
+
+// SIMD: 128-bit
+static int HW_SSE, HW_SSE2, HW_SSE3, HW_SSSE3, HW_SSE41, HW_SSE42, HW_SSE4a, HW_AES, HW_SHA;
+
+// SIMD: 256-bit
+static int HW_AVX, HW_XOP, HW_FMA3, HW_FMA4, HW_AVX2;
+
+// SIMD: 512-bit
+static int HW_AVX512F; // AVX512 Foundation
+static int HW_AVX512CD; // AVX512 Conflict Detection
+static int HW_AVX512PF; // AVX512 Prefetch
+static int HW_AVX512ER; // AVX512 Exponential + Reciprocal
+static int HW_AVX512VL; // AVX512 Vector Length Extensions
+static int HW_AVX512BW; // AVX512 Byte + Word
+static int HW_AVX512DQ; // AVX512 Doubleword + Quadword
+static int HW_AVX512IFMA; // AVX512 Integer 52-bit Fused Multiply-Add
+static int HW_AVX512VBMI; // AVX512 Vector Byte Manipulation Instructions
+
+// https://stackoverflow.com/questions/6121792/how-to-check-if-a-cpu-supports-the-sse3-instruction-set
+void check_cpu_features(void) {
+ int info[4];
+ cpuid(info, 0);
+ int nIds = info[0];
+
+ cpuid(info, 0x80000000);
+ unsigned nExIds = info[0];
+
+ // Detect Features
+ if (nIds >= 0x00000001) {
+ cpuid(info, 0x00000001);
+ HW_MMX = (info[3] & ((int)1 << 23)) != 0;
+ HW_SSE = (info[3] & ((int)1 << 25)) != 0;
+ HW_SSE2 = (info[3] & ((int)1 << 26)) != 0;
+ HW_SSE3 = (info[2] & ((int)1 << 0)) != 0;
+
+ HW_SSSE3 = (info[2] & ((int)1 << 9)) != 0;
+ HW_SSE41 = (info[2] & ((int)1 << 19)) != 0;
+ HW_SSE42 = (info[2] & ((int)1 << 20)) != 0;
+ HW_AES = (info[2] & ((int)1 << 25)) != 0;
+
+ HW_AVX = (info[2] & ((int)1 << 28)) != 0;
+ HW_FMA3 = (info[2] & ((int)1 << 12)) != 0;
+
+ HW_RDRAND = (info[2] & ((int)1 << 30)) != 0;
+ }
+ if (nIds >= 0x00000007) {
+ cpuid(info, 0x00000007);
+ HW_AVX2 = (info[1] & ((int)1 << 5)) != 0;
+
+ HW_BMI1 = (info[1] & ((int)1 << 3)) != 0;
+ HW_BMI2 = (info[1] & ((int)1 << 8)) != 0;
+ HW_ADX = (info[1] & ((int)1 << 19)) != 0;
+ HW_SHA = (info[1] & ((int)1 << 29)) != 0;
+ HW_PREFETCHWT1 = (info[2] & ((int)1 << 0)) != 0;
+
+ HW_AVX512F = (info[1] & ((int)1 << 16)) != 0;
+ HW_AVX512CD = (info[1] & ((int)1 << 28)) != 0;
+ HW_AVX512PF = (info[1] & ((int)1 << 26)) != 0;
+ HW_AVX512ER = (info[1] & ((int)1 << 27)) != 0;
+ HW_AVX512VL = (info[1] & ((int)1 << 31)) != 0;
+ HW_AVX512BW = (info[1] & ((int)1 << 30)) != 0;
+ HW_AVX512DQ = (info[1] & ((int)1 << 17)) != 0;
+ HW_AVX512IFMA = (info[1] & ((int)1 << 21)) != 0;
+ HW_AVX512VBMI = (info[2] & ((int)1 << 1)) != 0;
+ }
+ if (nExIds >= 0x80000001) {
+ cpuid(info, 0x80000001);
+ HW_x64 = (info[3] & ((int)1 << 29)) != 0;
+ HW_ABM = (info[2] & ((int)1 << 5)) != 0;
+ HW_SSE4a = (info[2] & ((int)1 << 6)) != 0;
+ HW_FMA4 = (info[2] & ((int)1 << 16)) != 0;
+ HW_XOP = (info[2] & ((int)1 << 11)) != 0;
+ }
}
-int is_fma_avx() {
+int is_avx() {
static int result = -1;
if (result == -1) {
- result = simd_detect_x86(AVXFlag);
+ check_cpu_features();
+ result = HW_AVX;
if (result == 1) printf(" Used AVX \n");
else printf(" Not used AVX \n");
}
return result;
}
+int is_fma_avx2() {
+ static int result = -1;
+ if (result == -1) {
+ check_cpu_features();
+ result = HW_FMA3 && HW_AVX2;
+ if (result == 1) printf(" Used FMA & AVX2 \n");
+ else printf(" Not used FMA & AVX2 \n");
+ }
+ return result;
+}
+
// https://software.intel.com/sites/landingpage/IntrinsicsGuide
void gemm_nn(int M, int N, int K, float ALPHA,
float *A, int lda,
@@ -401,7 +483,7 @@
float *C, int ldc)
{
int i, j, k;
- if (is_fma_avx() == 1) { // AVX
+ if (is_avx() == 1) { // AVX
for (i = 0; i < M; ++i) {
for (k = 0; k < K; ++k) {
float A_PART = ALPHA*A[i*lda + k];
@@ -875,7 +957,7 @@
int channels_col = channels * ksize * ksize;
// optimized version
- if (height_col == height && width_col == width && stride == 1 && pad == 1 && is_fma_avx())
+ if (height_col == height && width_col == width && stride == 1 && pad == 1 && is_fma_avx2())
{
#pragma omp parallel for
for (c = 0; c < channels_col; ++c) {
@@ -954,6 +1036,29 @@
}
}
+void transpose_8x8_bits(unsigned char A[8], unsigned char B[8], int m, int n)
+{
+ unsigned x, y, t;
+
+ // Load the array and pack it into x and y.
+
+ x = (A[0] << 24) | (A[m] << 16) | (A[2 * m] << 8) | A[3 * m];
+ y = (A[4 * m] << 24) | (A[5 * m] << 16) | (A[6 * m] << 8) | A[7 * m];
+
+ t = (x ^ (x >> 7)) & 0x00AA00AA; x = x ^ t ^ (t << 7);
+ t = (y ^ (y >> 7)) & 0x00AA00AA; y = y ^ t ^ (t << 7);
+
+ t = (x ^ (x >> 14)) & 0x0000CCCC; x = x ^ t ^ (t << 14);
+ t = (y ^ (y >> 14)) & 0x0000CCCC; y = y ^ t ^ (t << 14);
+
+ t = (x & 0xF0F0F0F0) | ((y >> 4) & 0x0F0F0F0F);
+ y = ((x << 4) & 0xF0F0F0F0) | (y & 0x0F0F0F0F);
+ x = t;
+
+ B[0] = x >> 24; B[n] = x >> 16; B[2 * n] = x >> 8; B[3 * n] = x;
+ B[4 * n] = y >> 24; B[5 * n] = y >> 16; B[6 * n] = y >> 8; B[7 * n] = y;
+}
+
void activate_array_cpu_custom(float *x, const int n, const ACTIVATION a)
{
int i = 0;
@@ -961,7 +1066,7 @@
{}
else if (a == LEAKY)
{
- if (is_fma_avx()) {
+ if (is_fma_avx2()) {
__m256i all256_sing1 = _mm256_set_epi32(0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000);
__m256 all256_01 = _mm256_set1_ps(0.1F);
--
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